       
FRASER'S HILL
Copyright © Fraser's Hill Ltd. 1990-1994.
All Rights Reserved. HARDWARE CONFIGURATION The FHL-7135 has two switches and two jumper blocks which are used to configure the board. These switches and jumpers are located as follows.
S1: PC I/O Base Address
Switch S1 sets the base PC I/O address for accessing the FHL-7135 adapter card. The following table lists the valid switch settings and the corresponding PC I/O base address.
position 1 2 3 4 i/o
address bit A8 A7 A6 A5 addr
on on on on 0200
on on on off 0220
on on off on 0240
on on off off 0260
on off on on 0280
on off on off 02A0
on off off on ----
on off off off ----
off on on on 0300
off on on off 0320
off on off on 0340
off on off off 0360
off off on on 0380
off off on off 03A0
off off off on ----
off off off off ----
S2 - PC MEMORY WINDOW ADDRESSES
Switch S2 sets the PC memory addresses for the two 16 kilobyte windows into the FHL-7135 memory. Positions 1-4 set the PC memory address for Window 0; positions 5-8 set the PC memory address for Window 1. The following table lists the valid switch settings and the corresponding PC segment addresses.
WINDOW 0 WINDOW 1 1 2 3 4 addr 5 6 7 8 addr on on on on C000 on on on on ---- off on on on C400 off on on on C400 on off on on C800 on off on on C800 off off on on CC00 off off on on CC00 on on off on D000 on on off on D000 off on off on D400 off on off on D400 on off off on D800 on off off on D800 off off off on ---- off off off on DC00 on on on off E000 on on on off ---- off on on off ---- off on on off E400 on off on off E800 on off on off ---- off off on off ---- off off on off EC00 on on off off ---- on on off off ---- off on off off ---- off on off off ---- on off off off ---- on off off off ---- off off off off ---- off off off off ----J1 - PC INTERRUPT REQUEST LEVEL This jumper selects the PC IRQ used when the board microcode wants to interrupt the PC. Choices are IRQ2, IRQ3, IRQ4, IRQ5, and IRQ7.
This jumper selects the source (external or internal) for the synchronous clocking signals.
PRIMARY CHANNEL
DB15 V.35
SIGNAL CIRCUIT PIN PIN I/O
FG 01 A
SG 102 08 B
TXD(A) 103 09 P OUT
TXD(B) 103 02 S OUT
RXD(A) 104 11 R IN
RXD(B) 104 04 T IN
RTS 105 03 C OUT
CTS 106 05 D IN
DSR 107 06 E IN
DTR 108 15 H OUT
DCD 109 07 F IN
SCTE(A) 113 10 U OUT
SCTE(B) 113 12 W OUT
TXC(A) 114 10 Y IN
TXC(B) 114 12 AA IN
RXC(A) 115 14 V IN
RXC(B) 115 13 X IN
Notes:
The signals with (A) and (B) are the two parts of a balanced pair, not two channels. Jumper J2 controls the usage of the DB15 pin 10/12 pair. These pins are TXC connected to V.35 pins Y/AA when external clocking is selected, or SCTE connected to V.35 pins U/W when internal clocking is selected.
Fraser's Hill and FHL are registered trademarks of Fraser's Hill Ltd. Other product and company names may be registered trademarks, trademarks, or service marks of their respective owners. FHL 14-Apr-2002 
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