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FRASER'S HILL
FHL-7121
USER REFERENCE MANUAL
Revision 1.02

Copyright © Fraser's Hill Ltd. 1990-1994. All Rights Reserved.
Fraser's Hill and FHL are registered trademarks of Fraser's Hill Ltd.

HARDWARE CONFIGURATION

The FHL-7121 has two switches and three jumper blocks which are used to configure the board. These switches and jumpers are located as follows.

[7121A21]

S1: PC I/O Base Address
S2: PC Memory Window Address
J1: PC Interrupt Request Level
J2: Not Used
J3: Receive Data/Fail Safe
X.21 Signals

S1 - PC I/O BASE ADDRESS

Switch S1 sets the base PC I/O address for accessing the FHL-7121 adapter card. The following table lists the valid switch settings and the corresponding PC I/O base address.

position         1       2       3       4      i/o
address bit     A8      A7      A6      A5      addr

                on      on      on      on      0200
                on      on      on      off     0220
                on      on      off     on      0240
                on      on      off     off     0260
                on      off     on      on      0280
                on      off     on      off     02A0
                on      off     off     on      ----
                on      off     off     off     ----
                off     on      on      on      0300
                off     on      on      off     0320
                off     on      off     on      0340
                off     on      off     off     0360
                off     off     on      on      0380
                off     off     on      off     03A0
                off     off     off     on      ----
                off     off     off     off     ----
S2 - PC MEMORY WINDOW ADDRESSES

Switch S2 sets the PC memory addresses for the two 16 kilobyte windows into the FHL-7121 memory. Positions 1-4 set the PC memory address for Window 0; positions 5-8 set the PC memory address for Window 1. The following table lists the valid switch settings and the corresponding PC segment addresses.

WINDOW 0                             WINDOW 1
1     2     3     4      addr        5     6     7     8      addr

on    on    on    on     C000        on    on    on    on     ----
off   on    on    on     C400        off   on    on    on     C400
on    off   on    on     C800        on    off   on    on     C800
off   off   on    on     CC00        off   off   on    on     CC00
on    on    off   on     D000        on    on    off   on     D000
off   on    off   on     D400        off   on    off   on     D400
on    off   off   on     D800        on    off   off   on     D800
off   off   off   on     ----        off   off   off   on     DC00
on    on    on    off    E000        on    on    on    off    ----
off   on    on    off    ----        off   on    on    off    E400
on    off   on    off    E800        on    off   on    off    ----
off   off   on    off    ----        off   off   on    off    EC00
on    on    off   off    ----        on    on    off   off    ----
off   on    off   off    ----        off   on    off   off    ----
on    off   off   off    ----        on    off   off   off    ----
off   off   off   off    ----        off   off   off   off    ----
J1 - PC INTERRUPT REQUEST LEVEL

This jumper selects the PC IRQ used when the board microcode wants to interrupt the PC. Choices are IRQ2, IRQ3, IRQ4, IRQ5, and IRQ7.

J2 - NOT USED

This jumper is currently unused.

J3 - RECEIVE DATA FAIL SAFE

This jumper selects the state of the receive data signal when no cable is attached. This jumper should be left at the default configuration.
default: both shunts vertical
alternate: both shunts horizontal

X.21 SIGNALS

PRIMARY CHANNEL

       SIGNAL    CIRCUIT     PIN        I/O

        FG                   01
        TXD         T        02/09      OUT
        RXD         R        04/11      IN
        CTL         C        03/10      OUT
        IND         I        05/12      IN
        RXC         S        06/13      IN
        TXC         B        07/14      IN
        SG                   08
        NC                   15
Note: The signals with two pins are A/B of a balanced pair.



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Copyright © 1997-2008 Fraser's Hill Ltd. All rights reserved.
Fraser's Hill and FHL are registered trademarks of Fraser's Hill Ltd.
Other product and company names may be registered trademarks,
trademarks, or service marks of their respective owners.

FHL   14-Apr-2002